library verilog;
use verilog.vl_types.all;
entity Final_Permutation is
    port(
        Final_Permutation_Input: in     vl_logic_vector(64 downto 1);
        Final_Permutation_Select: in     vl_logic;
        Final_Permutation_Output: out    vl_logic_vector(64 downto 1);
        Final_Permutation_Finish_Flag: out    vl_logic;
        clk             : in     vl_logic
    );
end Final_Permutation;
